FPGA gateware
Colorlight AES67
AES67 + IEEE 1588 PTP fully in Verilog.
A complete AES67 / RAVENNA implementation on the Colorlight i9 v7.2 ECP5, with a custom 1 Gbps RGMII MAC that emits byte-precise SFD pulses, hardware PTP timestamping with cable-asymmetry compensation and a VexRiscv softcore running lwIP for the management plane.
Specifications
- Custom MAC with byte-precise SFD pulses for PTP capture
- Verilog PTP: NCO, packet processor, BMC-driven master/slave
- 125 µs packet time, 500 µs jitter buffer, cut-through router (~336 ns)
- Hardware DSP slot per channel: gain, mute, peak meter (Q1.15)
- lwIP DHCP / mDNS / httpd on the same wire as the RTP data path
- Single-page WebUI with live channel preview audio over /audio.wav
#fpga
#ecp5
#aes67
#ravenna
#ptp
#verilog
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